View CAT34AC02JA_416945.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Preliminary Information
CAT34AC02
2K-Bit SMBus EEPROM for ACR Card Configuration FEATURES
s 400 kHz (5V) and 100 kHz (1.8V) SMBus
H
GEN FR ALO
EE
LE
A D F R E ETM
s Self-timed write cycle with auto-clear s 1,000,000 program/erase cycles s 100 year data retention s 8-pin DIP, 8-pin SOIC and 8-pin TSSOP packages s 256 x 8 memory organization s Hardware write protect
compatible
s 1.8 to 6.0 volt operation s Low power CMOS technology
- zero standby current
s 16-byte page write buffer s Industrial, automotive and extended
temperature ranges
DESCRIPTION
The CAT34AC02 is a 2K-bit Serial CMOS EEPROM internally organized as 256 words of 8 bits each. Catalyst's advanced CMOS technology substantially reduces device power requirements. The CAT34AC02 features a 16-byte page write buffer. The device operates via the SMBus serial interface for ACR card configuration and is available in 8-pin DIP, 8-pin SOIC or 8-pin TSSOP packages.
PIN CONFIGURATION
DIP Package (P, L)
A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA A0 A1 A2 VSS
BLOCK DIAGRAM
SOIC Package (J, W)
EXTERNAL LOAD
1 2 3 4 8 7 6 5 VCC WP SCL SDA
DOUT ACK VCC VSS WORD ADDRESS BUFFERS
SENSE AMPS SHIFT REGISTERS
COLUMN DECODERS
TSSOP Package (U, Y)
A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA
MSOP Package (R, Z)
1 2 3 4 8 7 6 5
WP CONTROL LOGIC SDA START/STOP LOGIC
XDEC
E2PROM
PIN FUNCTIONS
Pin Name A0, A1, A2 SDA SCL WP VCC VSS Function Device Address Inputs Serial Data/Address Serial Clock Write Protect +1.8V to +6.0V Power Supply Ground
SCL A0 A1 A2 STATE COUNTERS SLAVE ADDRESS COMPARATORS HIGH VOLTAGE/ TIMING CONTROL DATA IN STORAGE
(c) 2003 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
1
Doc No. 1025, Rev. E
CAT34AC02
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias -55C to +125C Storage Temperature ....................... -65C to +150C Voltage on Any Pin with Respect to Ground(1) ........... -2.0V to +VCC + 2.0V VCC with Respect to Ground ............... -2.0V to +7.0V Package Power Dissipation Capability (TA = 25C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300C Output Short Circuit Current(2) ........................ 100mA RELIABILITY CHARACTERISTICS Symbol NEND(3) TDR
(3)
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
Parameter Endurance Data Retention ESD Susceptibility Latch-up
Reference Test Method
Min
Typ
Max
Units Cycles/Byte Years Volts mA
MIL-STD-883, Test Method 1033 1,000,000 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 100 2000 100
VZAP(3) ILTH(3)(4)
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
Symbol ICC ICC ISB
(5)
Parameter Power Supply Current (Read) Power Supply Current (Write) Standby Current (VCC = 5.0V) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage (VCC = 3.0V) Output Low Voltage (VCC = 1.8V)
Test Conditions fSCL = 100 kHz fSCL = 100 kHz VIN = GND or VCC VIN = GND to VCC VOUT = GND to VCC
Min
Typ
Max 1 3 0 10 10
Units mA mA A A A V V V V
ILI ILO VIL VIH VOL1 VOL2
-1 VCC x 0.7 IOL = 3 mA IOL = 1.5 mA
VCC x 0.3 VCC + 0.5 0.4 0.5
CAPACITANCE TA = 25C, f = 1.0 MHz, VCC = 5V Symbol CI/O(3) CIN
(3)
Parameter Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL)
Test Conditions VI/O = 0V VIN = 0V
Min
Typ
Max 8 6
Units pF pF
Note: (1) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to VCC +1V. (5) Standby Current (ISB) = 0A (<900nA).
Doc. No. 1025, Rev. E
2
CAT34AC02
A.C. CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
Read & Write Cycle Limits
1.8V-6.0V, 2.5V - 6.0V Symbol FSCL TI(1) t AA tBUF(1) tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR(1) tF(1) tSU:STO tDH Parameter Min Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SCL Low to SDA Data Out and ACK Out Time the Bus Must be Free Before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (for a Repeated Start Condition) Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time 4 100 4.7 4 4.7 4 4.7 0 50 1 300 Max 100 100 3.5
4.5V - 5.5V Units Min Max 400 100 1 1.2 0.6 1.2 0.6 0.6 0 50 0.3 300 0.6 100 kHz ns s s s s s s ns ns s ns s ns
Power-Up Timing(1)(2) Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Min Typ Max 1 1 Units ms ms
Write Cycle Limits Symbol tWR Parameter Write Cycle Time Min Typ 4 Max 5 Units ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
3
Doc No. 1025, Rev. E
CAT34AC02
FUNCTIONAL DESCRIPTION
The CAT34AC02 supports the SMBus data transmission protocol. This serial protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. Data transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT34AC02 operates as a Slave device. Both the Master and Slave devices can operate as either transmitter or receiver, but the Master device controls which mode is activated. A maximum of 8 devices may be connected to the bus as determined by the device address inputs A0, A1, and A2.
all data transfers into or out of the device. This is an input pin. SDA: Serial Data/Address The CAT34AC02 bidirectional serial data/address pin is used to transfer data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. A0, A1, A2: Device Address Inputs These inputs set device address when cascading multiple devices. A maximum of eight devices can be cascaded when using the device. WP: Write Protect This input, when tied to GND, allows write operations to the entire memory. For CAT34AC02 when this pin is tied to VCC, the entire array of memory is write protected. When left floating, memory is unprotected.
PIN DESCRIPTIONS
SCL: Serial Clock The CAT34AC02 serial clock input pin is used to clock Figure 1. Bus Timing
tF tLOW SCL tSU:STA tHD:STA tHD:DAT tHIGH tLOW
tR
tSU:DAT
tSU:STO
SDA IN tAA SDA OUT tDH tBUF
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT BYTE n
ACK tWR STOP CONDITION START CONDITION ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL START BIT STOP BIT
Doc. No. 1025, Rev. E
4
CAT34AC02
SERIAL BUS PROTOCOL
The following defines the features of the ACR Serial bus protocol: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT34AC02 monitor the SDA and SCL lines and will not respond until this condition is met. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition.
eight CAT34AC02 may be individually addressed by the system. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. After the Master sends a START condition and the slave address byte, the CAT34AC02 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT34AC02 then performs a Read or a Write operation depending on the state of the R/W bit. Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT34AC02 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each byte. When the CAT34AC02 begins a READ mode, it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT34AC02 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a START condition. The Master then sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 1011 for the CAT34AC02 (see Fig. 5). The next three significant bits (A2, A1, A0) are the device address bits and define which device the Master is accessing. Up to Figure 4. Acknowledge Timing
SCL FROM MASTER 1
8
9
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE
Figure 5. Slave Address Bits
1
0
1
1
A2
A1
A0
R/W
DEVICE ADDRESS
5
Doc No. 1025, Rev. E
CAT34AC02
WRITE OPERATIONS
Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the CAT34AC02. After receiving another acknowledge from the Slave, the Master device transmits the data byte to be written into the addressed memory location. The CAT34AC02 acknowledges once more and the Master generates the STOP condition, at which time the device begins its internal programming to nonvolatile memory. While this internal cycle is in progress, the device will not respond to any request from the Master device. Page Write The CAT34AC02 writes up to 16 bytes of data in a single write cycle, using the Page Write operation. The Page Write operation is initiated in the same manner as the Byte Write operation, however instead of terminating after the initial word is transmitted, the Master is allowed to send up to 15 additional bytes. After each byte has been transmitted the CAT34AC02 will respond with an acknowledge, and internally increment the low order address bits by one. The high order bits remain unchanged. If the Master transmits more than 16 bytes prior to sending the STOP condition, the address counter `wraps around', and previously transmitted data will be overwritten. Once all 16 bytes are received and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point all received data is written to the CAT34AC02 in a single write cycle. Acknowledge Polling The disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation, the CAT34AC02 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the CAT34AC02 is still busy with the write operation, no ACK will be returned. If the CAT34AC02 has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation.
WRITE PROTECTION
The write protection feature of CAT34AC02 allows the user to protect against inadvertent programming of the memory array. If the WP pin is tied to Vcc, the entire memory array is protected and becomes read only. If the WP pin is left floating or tied to Vss, the device can be written into.
Figure 6. Byte Write Timing
BUS ACTIVITY: MASTER SDA LINE
S T A R T S
SLAVE ADDRESS
BYTE ADDRESS
DATA
S T O P P
A C K
A C K
A C K
Figure 7. Page Write Timing
S T A R T S A C K S T O P P A C K A C K A C K A C K
BUS ACTIVITY: MASTER SDA LINE
SLAVE ADDRESS *
BYTE ADDRESS (n)
DATA n
DATA n+1
DATA n+P
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
Doc. No. 1025, Rev. E
6
CAT34AC02
READ OPERATIONS
The READ operation for the CAT34AC02 is initiated in the same manner as the write operation with the one exception that the R/W bit is set to a one. Three different READ operations are possible: Immediate Address READ, Selective READ and Sequential READ. Immediate Address Read The CAT34AC02's address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N+1. If N = 255 for the CAT34AC02, then the counter will `wrap around' to address 0 and continue to clock out data. After the CAT34AC02 receives its slave address information (with the R/W bit set to one), it issues an acknowledge, then transmits the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Selective Read Selective READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a `dummy' write operation by sending the START condition, slave address and byte address of the location it wishes to read. After the CAT34AC02 acknowledge the word address, the Master device resends the START condition Figure 8. Immediate Address Read Timing
S T A R T S A C K DATA N O A C K
and the slave address, this time with the R/W bit set to one. The CAT34AC02 then responds with its acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Sequential Read The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT34AC02 sends the initial 8-bit data requested, the Master will respond with an acknowledge which tells the device it requires more data. The CAT34AC02 will continue to output a byte for each acknowledge sent by the Master. The operation will terminate operation when the Master fails to respond with an acknowledge, thus sending the STOP condition. The data being transmitted from the CAT34AC02 is outputted sequentially with data from address N followed by data from address N+1. The READ operation address counter increments all of the CAT34AC02 address bits so that the entire memory array can be read during one operation. If more than the 256 bytes are read out, the counter will "wrap around" and continue to clock out data bytes.
BUS ACTIVITY: MASTER SDA LINE
SLAVE ADDRESS
S T O P P
K
SCL
8
9
SDA
8TH BIT DATA OUT NO ACK STOP
7
Doc No. 1025, Rev. E
CAT34AC02
Figure 9. Memory Array
FFH
Hardware Write Protectable (by connecting WP pin to Vcc)
00H
Figure 10. Selective Read Timing
S T A R T S A C K
*
BUS ACTIVITY: MASTER SDA LINE
SLAVE ADDRESS
BYTE ADDRESS (n)
S T A R T S A C K
SLAVE ADDRESS
S T O P P A C K DATA n N O A C K
5020 FHD F11
Figure 11. Sequential Read Timing
BUS ACTIVITY: MASTER SDA LINE A C K A C K A C K A C K N O A C K SLAVE ADDRESS DATA n DATA n+1 DATA n+2 DATA n+x
S T O P P
5020 FHD F12
Doc. No. 1025, Rev. E
8
CAT34AC02
ORDERING INFORMATION
Prefix CAT Device # 34AC02 J Suffix I -1.8 TE13
Optional Company ID
Product Number
Temperature Range I = Industrial (-40C to 85C) A = Automotive (-40C to 105C) E = Extended (-40C to 125C) Package P: PDIP J: SOIC (JEDEC) U: TSSOP R: MSOP L: PDIP (Lead free, Halogen free) W: SOIC (Lead free, Halogen free) Y: TSSOP (Lead free, Halogen free) Z: MSOP (Lead free, Halogen free)
Tape & Reel TE13: 2000/Reel
Operating Voltage Blank: 2.5V - 6.0V 1.8: 1.8V - 6.0V
Notes: (1) The device used in the above example is a 34AC02JI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage, Tape & Reel)
9
Doc No. 1025, Rev. E
Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP TM AE2 TM
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com
Publication #: Revison: Issue date: Type:
1025 E 5/9/03 Preliminary

▲Up To Search▲

Price & Availability of CAT34AC02JA

	To Download CAT34AC02JA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .